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71M6521DE/DH/FE Data Sheet
Bit
IP0.6
Symbol
WDTS
Function
Watchdog timer status flag. Set when the watchdog timer was started. Can be
read by software.
Table 32: The IP0 bit Functions (see also Table 45)
Note: The remaining bits in the IP0 register are not used for watchdog control
Watchdog Timer Reload Register ( WDTREL ):
MSB
LSB
7
6
5
4
3
2
1
0
Table 33: The WDTREL Register
Bit
WDTREL.7
WDTREL.6
to
WDTREL.0
Symbol
7
6-0
Function
Prescaler select bit. When set, the watchdog is clocked through an additional
divide-by-16 prescaler
Seven bit reload value for the high-byte of the watchdog timer. This value is
loaded to the WDT when a refresh is triggered by a consecutive setting of bits
WDT and SWDT .
Table 34: The WDTREL Bit Functions
The WDTREL register can be loaded and read at any time.
Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own request flag(s) located in a
special function register ( TCON, IRCON , and SCON ). Each interrupt requested by the corresponding flag can be
individually enabled or disabled by the enable bits in SFRs IEN0 , IEN1 , and IEN2 .
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other
parts of the 71M6521DE/DH/FE, for example the CE, DIO, RTC EEPROM interface.
Interrupt Overview
When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 53. Once interrupt
service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a
return from instruction, "RETI". When an RETI is performed, the MPU will return to the instruction that would have
been next when the interrupt occurred.
When the interrupt condition occurs, the MPU will also indicate this by setting a flag bit. This bit is set regardless of
whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, then samples are
polled by the hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt
request flag is set.
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Rev 3
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